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                           MPW shuttle time summary

 

 

 

MOSIS offers multiproject wafer (MPW) runs for the following IC fabricators. Designers need to plan design activities to meet the schedule constraints. Participants on Globalfoundries MPW runs must adhere to the timeline. To be considered ontime for MPW runs in all other processes, layout and paperwork are due to MOSIS by 1 PM PT (Pacific/California Time) on the date listed.

Globalfoundries Fabrication Schedule

Participants on Globalfoundries MPW runs must adhere to the timeline.

The Globalfoundries fabrication processes available through MOSIS include 0.35 µm,0.18 µm, 0.13 µm, 65 nm CMOS , and 28 nm CMOS processes. Access is limited to MOSIS commercial account holders who are approved by Globalfoundries. Globalfoundries MPW maximum die size allowed is 12.5 mm x 12.5 mmTo start the approval process, please send your request to the MOSIS Customer Support System.

Globalfoundries (GF) featured CMOS processes:

28 nm40 nm65 nm0.13 µm0.18  µm, and 0.35 µm.

 

IBM Fabrication Schedule

IBM featured processes

SiGe: 8HP (0.13 µm), 8XP (0.13 µm), and 7WL (0.18 µm) 
CMOS: 8RF-DM (0.13 µm) 

SOI: 7RF SOI (0.18 µm)


Access is limited to MOSIS commercial account holders who are approved by IBM. To create an account and request design kit and related documents, follow the IBM document access instructions. Existing accounts can skip the first step, "Commercial Account Application."

IBM Multi-Project Wafer (MPW) Run Processes

These processes are available for Multi-Project Wafer (MPW) Runs or Dedicated (COT) Runs.

IBM Dedicated Run (COT) Processes

These processes are available for Dedicated (COT) runs.

IBM Trusted Foundry Run Processes

These processes are available for Dedicated (COT) or DoD/Trusted Foundry runs.

TSMC Fabrication Schedule

TSMC featured processes

40 / 45 nm65 nm90 nm, 0.18µm, 0.35µm and TinyChip

p Projected


(5) Access restricted to university accounts. 
(7) Supported voltages: 1.8/3.3/32 
(10) Supported voltages: 3.3,/20/23/Vg3.3V, 3.3/5/12/15/20/40/Vg3.3/5.12V 
(16) BCD 
(17) BCD Gen-2 

Dedicated (COT) runs through MOSIS are also available in the above processes. Dedicated runs can be scheduled to start at any time. 

austriamicrosystems (AMS) Fabrication Schedule

AMS featured processes:

0.18 µm in both CMOS and HV CMOS 
0.35 µm

Fabrication Schedule

The imec-ePIXfab MPW runs are listed below. To be considered ontime for an MPW run, layout and paperwork are due to MOSIS by 1 PM PT (Pacific/California Time) on that date.

imec-ePIXfab SiPhotonics Full Platform (Advanced Passives + Modulator + Detector + Heater)

  • July 1, 2014: Project Registration due 
    August 4, 2014: DRC-clean layout due at MOSIS
  • November 3, 2014: Project Registration due 
    December 3, 2014: DRC-clean layout due at MOSIS

imec-ePIXfab SiPhotonics Passives

  • March 24th, 2014
  • September 1st, 2014
  • December 1st, 2014