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III-V 特殊工艺
器件模型
ICC
主页
MOSIS owned IP:
Digital Group
  1. ARM Bus Controller
  2. HDMI Controller
  3. MIPI Controller
  4. USB 2.0 Controller
  5. USB 3.0 Controller
  6. PCIe Controller
  7. DDR Controller
  8. Video Controllers
  9. Ethernet Controller
  10. I2C Controller
  11. JPEG Encoders
  12. Non-Volatile Memory Instance
  13. Memory Compilers
  14. Register Files
  15. RAD-HARD Memory Instances
  16. Custom Digital Libraries
  17. Custom I/O Libraries
  18. AC97 Audio Controller
  19. MAC 10/100/1000 Ethernet Controller
  20. PCI 32 Bridge Controller
  21. SDRAM/FLASH/SRAM Memory Controller
Core Group (CPU & DSP)
  1. 8051
  2. 80168
  3. 68k
  4. BA22 Embedded 32 bit RISC/DSP Core
  5. BA14 Embedded processor
  6. BA12 Embedded processor
  7. GPS
  8. FPS6 32 bit general purpose CPU
  9. APS3S 32 bit general purpose CPU
  10. APS3F 32 bit general purpose CPU
  11. APS3B 32 bit general purpose CPU
  12. 16bit DSP core
INTERFACE GROUP (Controller & PHY)
  1. HDMI
  2. USB2.0 (host & device)
  3. MIPI
  4. PCI2
  5. PCIe
  6. Ethernet10 &100
  7. AMBA4
  8. DDR & DDR2
  9. SERDES
  10. LVDS (Transmitter & Receiver)
  11. Bluetooth 2.1 =EDR PHY & Baseband
ANALOG GROUP
  1. Clock Generation Group (PLL & DLL, OSC)
  2. Data Converter Group (ADC, DAC, Sigma-Delta ADC, Sigma-Delta DAC)
  3. Power Converter Group (Bandgap, Power-on-Reset, Voltage Regulator, OpAmp)

Standard Cells, IP:


Standard cell libraries enabling synthesis to place and route design flows are available for selected processes.


ARM

Standard cell libraries, I/Os (pads), and memory generators for various processes are available from ARM; university support for these libraries is available through MOSIS.


Aragio

MOSIS commercial customers can contact Aragio directly. Universities can access Aragio front-end view I/O cells for the IBM 10LPe process through MOSIS.

Virage

Standard cells and memories for the IBM 10LPe/RFe process are available from Virage Logic for MOSIS commercial and academic customers.

ChipEstimate.com

ChipEstimate.com is a resource for chip size estimation and available IP.