Yuan Li received the Ph.D. degree in Electrical Engineering of Beijing University of Technology. She was a Visiting Scholar with Semiconductor Power Electronics Center (SPEC), The University of Texas at Austin, Austin, TX, USA. She is currently an associate Professor and a Member of the State Key Laboratory of Wide-Bandgap Semiconductor Devices and Integrated Technology, Xidian University. Her current research interests include GaN, SiC and Ga2O3 power devices’ thermoelectric characteristics, dynamic characteristics and reliability. In the past five years, she has published 7 high-level journal articles (IEEE Transactions on Power Electronics, IEEE Journal of Emerging and Selected Topics in Power Electronics, IEEE ISPSD, IEEE Transactions on Electron Devices) and applied for 15 invention patents; She hosted the National Natural Science Foundation of China, the National 21X Project, the Shaanxi Province Thousand Talents Plan project. She was the core participation in one major special project of the National 21X Project 1 Project, etc. She serves as the guest research fellow of National Key Laboratory of Intense Pulsed Radiation Simulation and Effect and the ICREED 2023 TPC Member. Her research results actively serve the industry, creating economic value for listed companies related to the new energy industry, such as Hongwei Technology, Xinwangda, Nanrui Jibao, etc.

Abstract: Currently, the published Ga2O3 MOS-Type trench diodes all use [010] trench sidewall with low thermal conductivity (kT[100]) but rarely [100] trench sidewall with high thermal conductivity (kT[010]). In fact, even if wet etching is used to repair the trench side wall, the side-wall-orientationdependent etch damage still increases gradually with the increase of trench angle ([010] trench as 0° rotation). For the first time, the optimized sidewall interface quality (OSIQ) strategy based on the ferroelectric material of PZT is applied to Ga2O3 trench diode (PSTD) to improve the trench sidewall interface quality for all trench-angle devices, which has verified OSIQ and its related electro-thermal optimization. The increasing trend of current density with different pre-voltage stress and pre-voltage stress time of PSTD are exhaustively investigated, and the [100] one shows the more improved and advantageous current rate compared to [010] one with the same chip size after the stress. Further, the mechanism of the proposed OSIQ has been revealed. This work can give aids to comprehensive improvement of electro-thermal performance of Ga2O3 trench device. 

2010 to 2014, he was a Professor with Center for Spintronics Integrated Systems, Tohoku University, Sendai,  Japan. His research theme during the period was spintronics devices including STT-MRAM. From 2017 to  2024, he was a Professor with Graduate School of Information, Production and Systems, Waseda University,  Kitakyushu, Japan, where he worked on STT-MTJ device modeling for SPICE and Deep Neural Network  (DNN) inference accelerators based on in-memory computing architecture. In 2024, he joined Unisantis  Electronics Singapore Pte. Ltd. and is engaged in research and development of novel single transistor  memories.  

Abstract: A major performance bottleneck of modern computers in von Neumann architecture is the data communication between the CPU and off-chip memories. To mitigate this issue, more and more memories are merged with the CPU as caches. However, SRAM exhibits serious issues when it is implemented in large-scale last level caches; large standby current and latency overhead due to long signal and data wires which is attributed to  a large memory macro size. There have been several attempts to use 1T1C DRAMs as embedded cache memories. However, this  also faces some problems; the cell process is not compatible with standard CMOS and secondly exotic material is needed for the capacitor. Furthermore, the transistor performance of CPU degrades because the CMOS transistor process is followed by the fabrication process of the stacked capacitor with a large thermal budget. We propose a memory named KFBM using a novel single transistor cell for large-scale cache applications. Though it requires an additional process to the standard CMOS one, the cell process precedes  the CMOS transistor process and no new material is necessary for the cell. The cell size is smaller than the embedded DRAM. In this talk, we present the cell’s concept, structure and operations with electrical characteristics obtained by TCAD simulations.

Andries J. Scholten received the M.Sc. degree and Ph.D. degrees in physics from the University of Utrecht, The Netherlands. Andries joined Philips Research Laboratories in August 1996, which be-came NXP in 2006. In his work at Philips/NXP, he has co-developed and industrialized the well-known compact models ‘MOS Model 9’, ‘MOS Model 11’, ‘JUNCAP2’, and ‘PSP’. Andries is IEEE and NXP fellow.

Abstract: Self-heating of advanced CMOS devices, such as FinFETs and FDSOI transistors, is becoming more and more important due to ever increasing power densities. An elegant experimental method to characterize self-heating is the so-called ‘AC conductance technique’. This talk will explain the background of this technique, its underlying assumptions, as well as its pros and cons. Several examples on state-of-the-art semiconductor devices will be given.

Maria Helena Fino is associate professor at NOVA FCT-School of Science and Tecnology in Portugal. She is now the head of the Electrotechnical and Computer engineering. She got her Phd in Electronics in 1995. Since then she has devoted her teaching activity and research to the development of models and tools for the automatic design of analog circuits. Her teaching activities include a master course dedicated to the use of EDA tools and the development of analitical models for nanoelectronic devices such as thin film transistors.

Abstract: Over the last decades the unprecedent evolution in material science has fueled the development of new nanodevices capable of supporting the development of new circuits and systems operating at higher frequency ranges and with reduced power consumption. However, the development of new nanodevices is supported by material science professionals while electronic engineers are responsible for the implementation of circuits/systems integrating these devices. At the academic level, there is an urgent need for graduating professionals capable of bridging the gap between the design of the nanodevices and their integration into circuits capable of taking advantages of the devices characteristics to keep pushing forward the circuits/systems performances. 

Chong Li obtained an MSc with distinction from the University of Manchester in 2007 and a PhD from the University of Glasgow in 2012. He is a Professor of Microwave Engineering at the University of Glasgow, where he leads the Microwave and Terahertz Electronics (MaTE) research group. His research interests include the design, modelling, fabrication, and characterisation of III-V compound semiconductor devices and their applications in wireless communications, quantum computing systems, and metrology. He has more than 100 publications including “the 2023 Terahertz Science and Technology Roadmap” and “Terahertz electronic devices” in “Springer Handbook of Semiconductor Devices” and 3 patents.

Professor Li began his academic career as a Research Assistant in 2011, progressing to Research Associate at the University of Glasgow until 2014 when he joined the UK's National Physical Laboratory. In 2017, he returned to the University of Glasgow as a Lecturer. He was promoted to Senior Lecturer in 2021 and to Professor of Microwave Engineering in 2023. Prof. Li is the Director of the Centre for Advanced Electronics (CAE) at the University of Glasgow, an executive member of ARFTG, the Co-Chair of the European Microwave Integrated Circuit (EuMiC) 2026, and the Chair of the ARFTG 2026 Spring conference. He was a visiting researcher at the University of Surrey in 2017, a member of the European Microwave Association (EuMA) representing the United Kingdom, Ireland, Gibraltar, and Malta from 2018 to 2021, and the Chair of Workshops & Short Courses for EuMW in 2021.

Abstract: Noise plays a crucial role in electronic devices, particularly in the front ends of RF/microwave systems such as mobile/wireless communications, radar, and imaging. Noise affects not only the sensitivity of receivers but also the transmit power of transmitters. Although high electron mobility transistors (HEMTs) have been the workhorses for these applications for many years, the noise sources and mechanisms within HEMTs are still not well understood, especially at very high frequencies (e.g., above 100 GHz) and extremely low temperatures (e.g., below 10 K). This paper discusses various noise theories related to HEMTs, including lattice scattering, phonon black-body radiation, and real space transfer often observed in GaAs/InP materials, with a focus on GaN HEMTs, where noise is likely generated by different mechanisms.

Juin J. Liou received the B.S. (honors), M.S., and Ph.D. degrees in electrical engineering from the University of Florida, Gainesville, in 1982, 1983, and 1987, respectively. In 1987, he joined the Department of Electrical and Computer Engineering at the University of Central Florida (UCF), Orlando, Florida where he held the positions of Pegasus Distinguished Professor, Lockheed Martin St. Laurent Professor, and UCF-Analog Devices Fellow. Dr. Liou is currently a chair professor at North Minzu University, China. Dr. Liou’s research interests are electrostatic discharge (ESD) protection design, modeling and simulation, and characterization. 

Abstract: Electrostatic discharge (ESD) is one of the most prevalent threats to the reliability of electronic components. It is an event in which a finite amount of charge is transferred from one object (i.e., human body) to the other (i.e., microchip). This process can result in a very high current passing through the microchip within a very short period of time, and hence more than 35% of chip damages can be attributed to the ESD event.  This is a problem with increasing significance in modern and future nanoscale technologies in the context of diminishing device dimensions. As such, designing on-chip ESD structures to protect integrated circuits against the ESD stress is a high priority in the semiconductor industry. The continuing advancement in MOS and emerging technologies makes the ESD-induced failures even more prominent, and one can predict with certainty that the availability of effective and robust ESD protection solutions will become increasingly critical and essential to the well-being of modern and future consumer products. In fact, many semiconductor companies worldwide are having difficulties in meeting the increasingly stringent ESD protection requirements for various electronics applications. This issue is further compounded by the fact that an industry standard electron design automation (EDA) tool for ESD applications is not yet commercially available.

An overview on the ESD protection schemes and testing will first be given in this talk. This is followed by presenting the development of an electron device compact model which enables circuit simulation under ESD conditions. Then another compact model which can be used to predict the ESD-induced junction failure in semiconductor devices will be addressed. Aspects of equivalent circuits, parameters, and results of the compact models will be given. Experimental data will be included in support of the models developed.    

Filip Tavernier is an associate professor at the Department of Electrical Engineering at KU Leuven in the MICAS research division. He is leading the research on the CMOS integration of novel optical communication circuits, high-performance data converters, DC-DC converters, and cryogenic circuits. Filip is a member of the European Solid-State Circuits Conference (ESSCIRC) and Custom Integrated Circuits Conference (CICC) technical program committees. He is the treasurer of the SSCS Benelux Chapter and SSCS Webinar Program Chair.

Abstract:  Advances in quantum technology and experimental physics have exponentially increased interest in circuits and systems capable of operating at extremely low temperatures. The 65-nm bulk CMOS technology is still one of the most widely used for analog and mixed-signal circuit design and shows excellent performance for cryogenic integrated circuit design. A simple and robust re-centering technique can address the absence of reliable foundry models at cryogenic temperature. Combining this technique with sufficient gate geometries results in a scalable compact model, fully restoring degrees of freedom in circuit design.

Professor Kiat Seng YEO (M’00–SM’09–F’16) received his B.Eng. (EE) in 1993, and Ph.D. (EE) in 1996 both from Nanyang Technological University (NTU), Singapore. Currently, he is a distinguished professor and a member of the Academic Council at Tianjin University. Before joining Tianjin University, he was Chairman of the University Research Board, Associate Provost for Research, Founding Associate Provost for Graduate Studies, and Founding Associate Provost for International Relations at SUTD. He has over 30 years of experience in industry, academia, and consultancy. Before joining SUTD, he was full professor at NTU; and spent 13 years in management positions as Associate Chair (Research), Head of Circuits and Systems and Sub-Dean (Students Affairs). Professor Yeo was also a Fellow of the Renaissance Engineering Programme (REP) and served as Senator and Advisory Board Member at NTU. He has made many outstanding contributions to advance Singapore’s education and research ambitions over the course of his career. As the Founding Director of VIRTUS, a SGD 52 million IC Design Centre of Excellence jointly set up by NTU and Singapore Economic Development Board (EDB), he contributed extensively to the economic development of integrated circuit design in Singapore by leading multidisciplinary research, with a focus on industry collaboration. In 2016, he initiated the FIRST (Fostering Industrial Research Success Together) Industry Workshop at SUTD. Today, it is a flagship event with an attendance of over 1,000 professionals from the industry. 

Abstract: The invention of the transistor in 1948 at Bell Laboratories was a turning point in the history of electronics. The transistor promises to revolutionize electronics; indeed, it has become an integral and essential part of our life. This keynote begins with an introduction to early computers, the invention of integrated circuits and how it changes the electronics industry. A key aspect of chip design is the characterization and modelling of passive devices. For example, physical design parameter optimization of on-chip inductors is performed to achieve similar inductance values as an experimental control to investigate how its core diameter, conductor spacing, and width affect their peak quality factors. The use of these optimized inductors is demonstrated to enhance the circuit characteristics of a giga-hertz amplifier.

While metallization in the form of inductors are “friends” that store magnetic energy, as interconnects, they are however, “foes” to RF/mm-wave IC designers.  Without considering these parasitics from interconnects in the design phase, fabricated RF/mm-wave circuits suffer power loss and shifts in circuit operating frequencies. A new figure of merit, intrinsic factor, IF, has been proposed in this research work to provide a convenient quantitative indication as to how interconnects affect the performance of RF/mm-wave ICs. As a conclusion, the other trends to watch for the next revolution will be presented.

Dr. Yang Li, born in April 1990, is an associate professor and master’s supervisor at the School of Integrated Circuit, Jiangnan University. He received his bachelor’s degree from Xi’an University of Electronic Science and Technology in 2012 and his Ph.D. from the same institution in 2017. He has been engaged in research on microwave wireless energy transmission devices, circuits, and systems at Tokushima University in Japan, Xidian University, and Jiangnan University.

He has participated in or led projects such as the National Key Research and Development Program, the Key R&D Project of Jiangsu Province, the Strategic Intelligence and Communication Research and Development Promotion Business (SCOPE) project, and the National Natural Science Foundation of China programs. In the past five years, he has published more than 40 journal/conference papers in international journals such as IEEE EDL, IEEE TED, IEEE TMTT, and has obtained 30 patents.

Abstract: Microwave wireless energy harvesting technology is considered one of the best methods for replenishing energy for micro-power Internet of Things systems such as battery-free sensors. By capturing, rectifying, and stabilizing the weak microwave energy in free space, the micro-power systems can be feed. Currently, there are many difficulties with microwave energy harvesting, with the greatest challenge being the realization of high-performance microwave-to-direct current (DC) conversion, i.e., microwave rectification. Existing microwave-to-DC conversion primarily relies on the Schottky diode scheme. However, due to the limitations of silicon material’s inherent properties, the conversion efficiency at 0 dBm is only about 60%, and when the input power is reduced to -20 dBm, the conversion efficiency is a mere 20%, which severely constrains system performance. Therefore, this report will discuss a microwave energy harvesting scheme based on Gallium Nitride Schottky diodes. Through unique diode design, precise modeling, and targeted rectifier circuit design, the comprehensive performance of the microwave energy harvesting system is enhanced.

Prof. Dr. Tiangui You received his PhD in Material Systems for Nanoelectronics from Technische Universität Chemnitz in 2016. During the period of doctoral study, he was also working as a guest scientist in Helmholtz Zentrum Dresden-Rossendorf and IFW Dresden. In 2016, he joined the XOI group in Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, and he was  promoted to professor in 2021. His research interest focuses on the heterogeneous integration materials and devices by ion-cutting technique. He has published more than 90 peer-reviewed journal papers. 

Abstract: Along with the developments of microelectronics and optoelectronics towards miniaturization and integration, the microsystem chips become more diversified and sophisticated, which has placed great demands on heterogeneous integration technology. Heterogeneous integration in turn will open up a new path for the development of microelectronics technology in the post-Moore era. Based on the current feature size, developing the heterogeneous materials and the integration of various functional devices will enable the functional diversification for a single-chip, especially for single-chip integration of optoelectronics, micro-energy, analog, RF, passive components and MEMS devices. The heterogeneous integrations of devices and systems are based on the heterogeneous integration materials. The traditional epitaxial growth methods, such as MBE, has play an important role in the heterogeneous integration materials, but the thin film quality is limited due to problems of lattice mismatch, inter-diffusion and antiphase domains. In order to break through the physical limitations of the traditional heteroepitaxial methods and to achieve a more flexible monocrystalline thin film heterogeneous integration, we introduce a heterogeneous integration material solution based on the ion-cutting technique. With this solution, a monocrystalline thin film in nanometer scale can be exfoliated from the single crystal wafer and transferred to any handle substrate, which provides a simple and efficient approach for wafer-scale high quality heterogeneous integration materials, e.g., InP-on-Si. With the regrowth of III-V on the InP-on-Si heterogeneous substrate, the integrated lasers on Si substrate can be achieved. Using this approach, we achieved state-of-the-art performance of the electrically-pumped, continuous-wave (CW) 1.55-µm Si-based laser with a room-temperature threshold current density of 0.65 kA/cm-2, and output power exceeding 155 mW per facet without facet coating in CW mode. CW lasing at 120℃ and pulsed lasing at over 130℃ were achieved. This generic approach is also applied to other material systems to provide better performance and more functionalities for photonics and microelectronics.

Wladek Grabinski, PhD , is an expert in electron technology with a focus on nano CMOS electrical characterization and compact/Verilog-A model development, parameter extraction and SPICE Lib validation. His career spans roles at ETHZ, EPFL, and Motorola/FSL. Currently, he is IHP consultant on SPICE/Verilog-A standardization and Open PDK for RF IC design enablement. He edited the reference book “Transistor Level Modeling for Analog/RF BiCMOS IC Design,” authored over 70 papers, and contributes to ESSDERC, MIXDES, LAEDC, and IEEE EDS committees, also managing MOS-AK Association since 1999.

Abstract: The semiconductor industry has been evolving and innovating for the past 75 years, ever since the first semiconductor transistor was invented. This rapid growth is driven by the direct and proactive contribution of the FOSS CAD/EDA to the entire technology flow: from state-of-the-art semiconductor technologies, device level compact/SPICE modeling, its VerilogA standardization to advanced IC designs for various HiTech applications. However, the semiconductor industry also faces many challenges in maintaining the growth of its workforce with skilled technicians and engineers. To address the increasing need for well-trained workers worldwide, we need to find innovative ways to attract skilled talent and strengthen the local semiconductor workforce ecosystem. The FOSS CAD/EDA tools with the recently available open access PDKs provide a new platform to connect IC design beginners, enthusiasts and experienced mentors to benefit from the collaboration opportunities enabled by the fast-growing open-source IC design movement. FOSS IC design collaboration is increasingly possible due to the rapid growth of open access PDKs recently offered by SkyWater, GF and IHP. This paper demonstrates the FOSS CAD/EDA contribution to the SPICE/Verilog-A modeling/standardization, compete IC design flow (Xschem, Qucs-S, ngspice, Xyce, OpenVAF, OpenEMS, Magic, kLayout, OpenRoad) as well as selected open source analog/RF and digital IC design examples